Contains definition of the interface to IDP modules.
The interface consists of 2 structures:
- definition of target assembler: ash
- definition of current processor: ph
These structures contain information about processor features, function pointers, etc.
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THREAD_SAFE bool | has_cf_chg (uint32 feature, uint opnum) |
| Does an instruction with the specified feature modify the i-th operand?
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THREAD_SAFE bool | has_cf_use (uint32 feature, uint opnum) |
| Does an instruction with the specified feature use a value of the i-th operand?
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idaman bool ida_export | has_insn_feature (int icode, uint32 bit) |
| Does the specified instruction have the specified feature?
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idaman bool ida_export | is_call_insn (const insn_t &insn) |
| Is the instruction a "call"?
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idaman bool ida_export | is_ret_insn (const insn_t &insn, bool strict=true) |
| Is the instruction a "return"?
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idaman bool ida_export | is_indirect_jump_insn (const insn_t &insn) |
| Is the instruction an indirect jump?
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idaman bool ida_export | is_basic_block_end (const insn_t &insn, bool call_insn_stops_block) |
| Is the instruction the end of a basic block?
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| CASSERT (sizeof(processor_t)==104) |
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idaman int ida_export | str2reg (const char *p) |
| Get any reg number (-1 on error)
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idaman int ida_export | is_align_insn (ea_t ea) |
| If the instruction at 'ea' looks like an alignment instruction, return its length in bytes. More...
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idaman ssize_t ida_export | get_reg_name (qstring *buf, int reg, size_t width, int reghi=-1) |
| Get text representation of a register. More...
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const char * | get_reg_info (const char *regname, bitrange_t *bitrange) |
| Get register information - useful for registers like al, ah, dil, etc. More...
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idaman bool ida_export | parse_reg_name (reg_info_t *ri, const char *regname) |
| Get register info by name. More...
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size_t | sizeof_ldbl (void) |
| Get size of long double.
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idaman bool ida_export | set_processor_type (const char *procname, setproc_level_t level) |
| Set target processor type. More...
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idaman char *ida_export | get_idp_name (char *buf, size_t bufsize) |
| Get name of the current processor module. More...
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idaman bool ida_export | set_target_assembler (int asmnum) |
| Set target assembler. More...
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bool | delay_slot_insn (ea_t *ea, bool *bexec, bool *fexec) |
| Helper function to get the delay slot instruction.
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void | gen_idb_event (idb_event::event_code_t code,...) |
| the kernel will use this function to generate idb_events
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#define | IDP_INTERFACE_VERSION 700 |
| The interface version number. More...
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#define | CF_STOP 0x00001 |
| Instruction doesn't pass execution to the. More...
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#define | CF_CALL 0x00002 |
| CALL instruction (should make a procedure here)
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#define | CF_CHG1 0x00004 |
| The instruction modifies the first operand.
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#define | CF_CHG2 0x00008 |
| The instruction modifies the second operand.
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#define | CF_CHG3 0x00010 |
| The instruction modifies the third operand.
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#define | CF_CHG4 0x00020 |
| The instruction modifies 4 operand.
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#define | CF_CHG5 0x00040 |
| The instruction modifies 5 operand.
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#define | CF_CHG6 0x00080 |
| The instruction modifies 6 operand.
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#define | CF_USE1 0x00100 |
| The instruction uses value of the first operand.
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#define | CF_USE2 0x00200 |
| The instruction uses value of the second operand.
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#define | CF_USE3 0x00400 |
| The instruction uses value of the third operand.
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#define | CF_USE4 0x00800 |
| The instruction uses value of the 4 operand.
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#define | CF_USE5 0x01000 |
| The instruction uses value of the 5 operand.
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#define | CF_USE6 0x02000 |
| The instruction uses value of the 6 operand.
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#define | CF_JUMP 0x04000 |
| The instruction passes execution using indirect. More...
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#define | CF_SHFT 0x08000 |
| Bit-shift instruction (shl,shr...)
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#define | CF_HLL 0x10000 |
| Instruction may be present in a high level. More...
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#define | CF_CHG7 0x020000 |
| The instruction modifies the 7th operand.
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#define | CF_CHG8 0x040000 |
| The instruction modifies the 8th operand.
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#define | CF_USE7 0x080000 |
| The instruction uses value of the 7th operand.
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#define | CF_USE8 0x100000 |
| The instruction uses value of the 8th operand.
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#define | AS_OFFST 0x00000001L |
| offsets are 'offset xxx' ?
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#define | AS_COLON 0x00000002L |
| create colons after data names ?
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#define | AS_UDATA 0x00000004L |
| can use '?' in data directives
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#define | AS_2CHRE 0x00000008L |
| double char constants are: "xy
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#define | AS_NCHRE 0x00000010L |
| char constants are: 'x
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#define | AS_N2CHR 0x00000020L |
| can't have 2 byte char consts
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#define | AS_1TEXT 0x00000040L |
| 1 text per line, no bytes
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#define | AS_NHIAS 0x00000080L |
| no characters with high bit
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#define | AS_NCMAS 0x00000100L |
| no commas in ascii directives
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#define | AS_HEXFM 0x00000E00L |
| mask - hex number format
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#define | ASH_HEXF0 0x00000000L |
| 34h
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#define | ASH_HEXF1 0x00000200L |
| h'34
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#define | ASH_HEXF2 0x00000400L |
| 34
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#define | ASH_HEXF3 0x00000600L |
| 0x34
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#define | ASH_HEXF4 0x00000800L |
| $34
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#define | ASH_HEXF5 0x00000A00L |
| <^R > (radix)
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#define | AS_DECFM 0x00003000L |
| mask - decimal number format
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#define | ASD_DECF0 0x00000000L |
| 34
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#define | ASD_DECF1 0x00001000L |
| #34
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#define | ASD_DECF2 0x00002000L |
| 34.
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#define | ASD_DECF3 0x00003000L |
| .34
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#define | AS_OCTFM 0x0001C000L |
| mask - octal number format
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#define | ASO_OCTF0 0x00000000L |
| 123o
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#define | ASO_OCTF1 0x00004000L |
| 0123
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#define | ASO_OCTF2 0x00008000L |
| 123
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#define | ASO_OCTF3 0x0000C000L |
| @123
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#define | ASO_OCTF4 0x00010000L |
| o'123
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#define | ASO_OCTF5 0x00014000L |
| 123q
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#define | ASO_OCTF6 0x00018000L |
| ~123
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#define | ASO_OCTF7 0x0001C000L |
| q'123
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#define | AS_BINFM 0x000E0000L |
| mask - binary number format
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#define | ASB_BINF0 0x00000000L |
| 010101b
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#define | ASB_BINF1 0x00020000L |
| ^B010101
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#define | ASB_BINF2 0x00040000L |
| %010101
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#define | ASB_BINF3 0x00060000L |
| 0b1010101
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#define | ASB_BINF4 0x00080000L |
| b'1010101
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#define | ASB_BINF5 0x000A0000L |
| b'1010101'
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#define | AS_UNEQU 0x00100000L |
| replace undefined data items with EQU (for ANTA's A80)
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#define | AS_ONEDUP 0x00200000L |
| One array definition per line.
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#define | AS_NOXRF 0x00400000L |
| Disable xrefs during the output file generation.
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#define | AS_XTRNTYPE 0x00800000L |
| Assembler understands type of extern symbols as ":type" suffix.
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#define | AS_RELSUP 0x01000000L |
| Checkarg: 'and','or','xor' operations with addresses are possible.
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#define | AS_LALIGN 0x02000000L |
| Labels at "align" keyword are supported.
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#define | AS_NOCODECLN 0x04000000L |
| don't create colons after code names
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#define | AS_NOSPACE 0x10000000L |
| No spaces in expressions.
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#define | AS_ALIGN2 0x20000000L |
| .align directive expects an exponent rather than a power of 2 More...
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#define | AS_ASCIIC 0x40000000L |
| ascii directive accepts C-like escape sequences More...
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#define | AS_ASCIIZ 0x80000000L |
| ascii directive inserts implicit zero byte at the end
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#define | AS2_BRACE 0x00000001 |
| Use braces for all expressions.
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#define | AS2_STRINV 0x00000002 |
| Invert meaning of idainfo::wide_high_byte_first for text strings. More...
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#define | AS2_BYTE1CHAR 0x00000004 |
| One symbol per processor byte. More...
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#define | AS2_IDEALDSCR 0x00000008 |
| Description of struc/union is in. More...
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#define | AS2_TERSESTR 0x00000010 |
| 'terse' structure initialization form More...
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#define | AS2_COLONSUF 0x00000020 |
| addresses may have ":xx" suffix More...
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#define | AS2_YWORD 0x00000040 |
| a_yword field is present and valid
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#define | PLFM_386 0 |
| Intel 80x86.
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#define | PLFM_Z80 1 |
| 8085, Z80
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#define | PLFM_I860 2 |
| Intel 860.
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#define | PLFM_8051 3 |
| 8051
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#define | PLFM_TMS 4 |
| Texas Instruments TMS320C5x.
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#define | PLFM_6502 5 |
| 6502
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#define | PLFM_PDP 6 |
| PDP11.
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#define | PLFM_68K 7 |
| Motorola 680x0.
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#define | PLFM_JAVA 8 |
| Java.
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#define | PLFM_6800 9 |
| Motorola 68xx.
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#define | PLFM_ST7 10 |
| SGS-Thomson ST7.
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#define | PLFM_MC6812 11 |
| Motorola 68HC12.
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#define | PLFM_MIPS 12 |
| MIPS.
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#define | PLFM_ARM 13 |
| Advanced RISC Machines.
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#define | PLFM_TMSC6 14 |
| Texas Instruments TMS320C6x.
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#define | PLFM_PPC 15 |
| PowerPC.
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#define | PLFM_80196 16 |
| Intel 80196.
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#define | PLFM_Z8 17 |
| Z8.
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#define | PLFM_SH 18 |
| Renesas (formerly Hitachi) SuperH.
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#define | PLFM_NET 19 |
| Microsoft Visual Studio.Net.
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#define | PLFM_AVR 20 |
| Atmel 8-bit RISC processor(s)
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#define | PLFM_H8 21 |
| Hitachi H8/300, H8/2000.
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#define | PLFM_PIC 22 |
| Microchip's PIC.
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#define | PLFM_SPARC 23 |
| SPARC.
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#define | PLFM_ALPHA 24 |
| DEC Alpha.
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#define | PLFM_HPPA 25 |
| Hewlett-Packard PA-RISC.
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#define | PLFM_H8500 26 |
| Hitachi H8/500.
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#define | PLFM_TRICORE 27 |
| Tasking Tricore.
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#define | PLFM_DSP56K 28 |
| Motorola DSP5600x.
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#define | PLFM_C166 29 |
| Siemens C166 family.
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#define | PLFM_ST20 30 |
| SGS-Thomson ST20.
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#define | PLFM_IA64 31 |
| Intel Itanium IA64.
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#define | PLFM_I960 32 |
| Intel 960.
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#define | PLFM_F2MC 33 |
| Fujistu F2MC-16.
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#define | PLFM_TMS320C54 34 |
| Texas Instruments TMS320C54xx.
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#define | PLFM_TMS320C55 35 |
| Texas Instruments TMS320C55xx.
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#define | PLFM_TRIMEDIA 36 |
| Trimedia.
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#define | PLFM_M32R 37 |
| Mitsubishi 32bit RISC.
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#define | PLFM_NEC_78K0 38 |
| NEC 78K0.
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#define | PLFM_NEC_78K0S 39 |
| NEC 78K0S.
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#define | PLFM_M740 40 |
| Mitsubishi 8bit.
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#define | PLFM_M7700 41 |
| Mitsubishi 16bit.
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#define | PLFM_ST9 42 |
| ST9+.
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#define | PLFM_FR 43 |
| Fujitsu FR Family.
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#define | PLFM_MC6816 44 |
| Motorola 68HC16.
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#define | PLFM_M7900 45 |
| Mitsubishi 7900.
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#define | PLFM_TMS320C3 46 |
| Texas Instruments TMS320C3.
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#define | PLFM_KR1878 47 |
| Angstrem KR1878.
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#define | PLFM_AD218X 48 |
| Analog Devices ADSP 218X.
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#define | PLFM_OAKDSP 49 |
| Atmel OAK DSP.
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#define | PLFM_TLCS900 50 |
| Toshiba TLCS-900.
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#define | PLFM_C39 51 |
| Rockwell C39.
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#define | PLFM_CR16 52 |
| NSC CR16.
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#define | PLFM_MN102L00 53 |
| Panasonic MN10200.
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#define | PLFM_TMS320C1X 54 |
| Texas Instruments TMS320C1x.
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#define | PLFM_NEC_V850X 55 |
| NEC V850 and V850ES/E1/E2.
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#define | PLFM_SCR_ADPT 56 |
| Processor module adapter for processor modules written in scripting languages.
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#define | PLFM_EBC 57 |
| EFI Bytecode.
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#define | PLFM_MSP430 58 |
| Texas Instruments MSP430.
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#define | PLFM_SPU 59 |
| Cell Broadband Engine Synergistic Processor Unit.
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#define | PLFM_DALVIK 60 |
| Android Dalvik Virtual Machine.
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#define | PLFM_65C816 61 |
| 65802/65816
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#define | PLFM_M16C 62 |
| Renesas M16C.
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#define | PLFM_ARC 63 |
| Argonaut RISC Core.
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#define | PLFM_UNSP 64 |
| SunPlus unSP.
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#define | PLFM_TMS320C28 65 |
| Texas Instruments TMS320C28x.
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#define | PLFM_DSP96K 66 |
| Motorola DSP96000.
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#define | PLFM_SPC700 67 |
| Sony SPC700.
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#define | PLFM_AD2106X 68 |
| Analog Devices ADSP 2106X.
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#define | PLFM_PIC16 69 |
| Microchip's 16-bit PIC.
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#define | PR_SEGS 0x000001 |
| has segment registers?
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#define | PR_USE32 0x000002 |
| supports 32-bit addressing?
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#define | PR_DEFSEG32 0x000004 |
| segments are 32-bit by default
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#define | PR_RNAMESOK 0x000008 |
| allow user register names for location names
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#define | PR_ADJSEGS 0x000020 |
| IDA may adjust segments' starting/ending addresses.
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#define | PR_DEFNUM 0x0000C0 |
| mask - default number representation
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#define | PRN_HEX 0x000000 |
| hex
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#define | PRN_OCT 0x000040 |
| octal
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#define | PRN_DEC 0x000080 |
| decimal
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#define | PRN_BIN 0x0000C0 |
| binary
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#define | PR_WORD_INS 0x000100 |
| instruction codes are grouped 2bytes in binary line prefix
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#define | PR_NOCHANGE 0x000200 |
| The user can't change segments and code/data attributes. More...
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#define | PR_ASSEMBLE 0x000400 |
| Module has a built-in assembler and will react to ev_assemble.
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#define | PR_ALIGN 0x000800 |
| All data items should be aligned properly.
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#define | PR_TYPEINFO 0x001000 |
| the processor module supports type information callbacks More...
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#define | PR_USE64 0x002000 |
| supports 64-bit addressing?
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#define | PR_SGROTHER 0x004000 |
| the segment registers don't contain the segment selectors.
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#define | PR_STACK_UP 0x008000 |
| the stack grows up
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#define | PR_BINMEM 0x010000 |
| the processor module provides correct segmentation for binary files More...
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#define | PR_SEGTRANS 0x020000 |
| the processor module supports the segment translation feature More...
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#define | PR_CHK_XREF 0x040000 |
| don't allow near xrefs between segments with different bases
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#define | PR_NO_SEGMOVE 0x080000 |
| the processor module doesn't support move_segm() More...
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#define | PR_USE_ARG_TYPES 0x200000 |
| use processor_t::use_arg_types callback
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#define | PR_SCALE_STKVARS 0x400000 |
| use processor_t::get_stkvar_scale callback
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#define | PR_DELAYED 0x800000 |
| has delayed jumps and calls More...
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#define | PR_ALIGN_INSN 0x1000000 |
| allow ida to create alignment instructions arbitrarily. More...
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#define | PR_PURGING 0x2000000 |
| there are calling conventions which may purge bytes from the stack
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#define | PR_CNDINSNS 0x4000000 |
| has conditional instructions
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#define | PR_USE_TBYTE 0x8000000 |
| BTMT_SPECFLT means _TBYTE type
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#define | PR_DEFSEG64 0x10000000 |
| segments are 64-bit by default
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#define | PR_OUTER 0x20000000 |
| has outer operands (currently only mc68k)
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#define | PR2_MAPPINGS 0x000001 |
| the processor module uses memory mapping
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#define | PR2_IDP_OPTS 0x000002 |
| the module has processor-specific configuration options
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#define | PR2_REALCVT 0x000004 |
| the module has 'realcvt' event implementation
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#define | PR2_THUMB_BIT 0x000008 |
| bit0 of code addresses has special meaning (arm thumb)
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#define | CUSTOM_INSN_ITYPE 0x8000 |
| Custom instruction codes defined by processor extension plugins must be greater than or equal to this.
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#define | REG_SPOIL 0x80000000L |
| processor_t::use_regarg_type uses this bit in the return value to indicate that the register value has been spoiled
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#define | OP_FP_BASED 0x00000000 |
| operand is FP based
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#define | OP_SP_BASED 0x00000001 |
| operand is SP based
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#define | OP_SP_ADD 0x00000000 |
| operand value is added to the pointer
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#define | OP_SP_SUB 0x00000002 |
| operand value is subtracted from the pointer
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